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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Slave Address
The device has a 7-bit long slave address (Figure 9). The
bit following the 7-bit slave address (bit eight) is the R/ W
bit, which is low for a write command and high for a read
command. The upper five bits of the slave address can-
not be changed and are always [01000]. Using the AD0
input, the lowest two bits can be programmed to assign
the device one of four unique slave addresses (see
Table 3). The device monitors the bus continuously, wait-
ing for a START condition followed by the device’s slave
address. When a device recognizes its slave address,
it acknowledges and is then ready for continued com-
munication.
Global Addressing and the Alert Reponse
Address (ARA)
The global address call is used in write mode to write to
the same register to multiple devices (address 60h). The
global address call can also be used in read mode (61h)
in the same way as the alert response address (ARA).
The actual alert response address (ARA) is 0Ch. The
MAX5980 slave device only responds to the ARA if its
INT (interrupt) output is asserted. All MAX5980 devices in
which the INT output is not asserted ignore the ARA.
When responding to the ARA, the device transmits a
byte of data on SDAOUT containing its own address in
the top 7 bits, and a 1 in the LSB (as does every other
device connected to the SDAIN line that has an active
interrupt). As each bit in the byte is transmitted, the
device determines whether to continue transmitting the
remainder of the byte or terminate transmission. The
device terminates the transmission if it sees a 0 on SDA
at a time when it is attempting to send a 1; otherwise it
continues transmitting bits until the entire byte has been
sent. This litigation protocol always allows the part with
the lowest address to complete the transmission, and the
microcontroller can respond to that interrupt. The device
deasserts INT if it completes the transmission of the
entire byte. If the device did not have the lowest address,
and terminates the transmission early, the INT output
remains asserted. In this way, the microcontroller can
continue to send ARA read cycles until all slave devices
successfully transmit their addresses, and all interrupt
requests are resolved.
General Call
In compliance with the I 2 C specification, the device
responds to the general call through global address 30h.
Message Format for Writing to the MAX5980
A write to the device comprises the device slave address
transmission with the R W bit set to 0, followed by at
least 1 byte of information. The first byte of information
is the command byte (Figure 10). The command byte
determines which register of the device is written to by
the next byte, if received. If the device detects a STOP
condition after receiving the command byte but before
receiving any data, then the device takes no further
action beyond storing the command byte.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the device selected by the command byte (Figure 11).
The control byte address then autoincrements (if pos-
sible; see Table 4) and then waits for the next data byte
or a STOP condition.
MSB
LSB
If multiple data bytes are transmitted before a STOP con-
SDA/
SDAIN
0
1
0
A3
A2
A1
A0
R/W
ACK
dition is detected, these bytes are stored in subsequent
MAX5980 internal registers as the control byte address
SCL
autoincrements (Figure 12). If the control byte address
can no longer increment, any subsequent data sent con-
tinues to write to that address.
Figure 9. Slave Address
CONTROL BYTE STORED ON STOP CONDITION
ACKNOWLEDGE FROM THE MAX5980
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
S
SLAVE ADDRESS
0
ACK
CONTROL BYTE
ACK
P
Figure 10. Write Format, Control Byte Received
24
R/W
ACKNOWLEDGE FROM THE MAX5980
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